A floating trap type nonvolatile memory device has the same structure as a MOS transistor, and uses multiple insulation layers including a tunnel insulation layer, a charge trap insulation layer, and a blocking insulation layer for gate insulation. The charge trap insulation layer is normally a silicon nitride layer. In the floating trap type nonvolatile memory device, to store data, electrons are injected into the charge trap insulation layer using Fowler-Nordheim (F-N) tunneling or hot carrier injection. On the other hand, data are erased by emitting electrons from the charge trap insulation layer or by injecting holes into the charge trap insulation layer.
Referring to FIG. 1, the floating trap type memory device comprises a gate electrode 20 disposed on a semiconductor substrate, a stacked multiple insulation layer 18 intervened between the gate electrode 20 and the semiconductor substrate 2, and source and drain regions 6 and 4 (respectively) formed in the semiconductor substrate of both sides of the gate electrode 20. The multiple insulation layer 18 includes a tunnel insulation layer 12, a charge trap insulation layer 14, and a blocking insulation layer 16, which are sequentially stacked. In a SONOS memory device that is a typical floating trap type memory device, the tunnel insulation layer 12 and the blocking insulation layer 16 are silicon oxide layers, and the charge trap insulation layer 14 is a silicon nitride layer. When a program voltage of about 10 to 20V is applied to the gate electrode 20, a ground voltage is applied to the source region 6, and a drain voltage of about 5 to 7V is applied to the drain region 4, hot carriers generated in the vicinity of the drain region are injected into the charge trap insulation 8 region of layer 14 adjacent to the drain region 4. As a result, a first bit is written.
FIGS. 2 and 3 are a top plan view and an equivalent circuit diagram, respectively, illustrating a nonvolatile memory device with a conventional NOR-type cell array structure.
Referring to FIG. 2, a cell array of a floating trap type nonvolatile memory device may have the same structure as a NOR-type cell array of a conventional nonvolatile memory device, such as a flash memory device. A typical NOR-type cell array structure includes a plurality of first active regions 28 disposed at a semiconductor substrate in parallel along an axis (vertical in FIG. 2) in one direction, and a plurality of second active regions 26 disposed in parallel along an axis (horizontal in FIG. 2) at right angles to that of the first active regions 28. Pairs of word lines wl are disposed between the second active regions 26 across the first active regions 28. A bit line plugs 24 is formed at the first active region 28 between a pair of the word lines wl. A plurality of bit lines bl crossing over the word lines wl are connected to the bit line plugs 24. A multiple insulation layer (18 of FIG. 1) is intervened between each word line wl and the first active region 28.
Referring to FIGS. 2 and 3, a typical NOR-type cell array includes a plurality of word lines wl disposed in parallel in one direction as well as a plurality of bit lines bl disposed at right angles to the word lines wl. A memory cell S1 is disposed in a region where the bit line bl and the word line wl cross each other. A drain of the memory cell S1 is connected to the bit line bl, a gate electrode is connected to the word line wl, and a source is grounded. Storing data in a selected memory cell S1 involves applying 5 to 7V to a selected bit line bl1 connected to the selected memory cell S1, then applying a voltage of 10 to 20V to a selected word line wl1. At this time, hot electrons generated in the vicinity of the drain of the selected memory cell S1 are injected into the charge trap insulation layer, thereby writing a first bit bl. With respect to the foregoing conventional NOR-type cell array, because the source and drain regions of the memory cell have an asymmetric structure, it is difficult to form a 2-bit programmable memory cell due to differences in capacitance and resistance between the source and drain regions. Accordingly, the conventional NOR-type cell array may store only 1 bit in each memory cell S1.
Recently, multi-bit memory cells have been proposed to form high-capacity memory devices without increasing physical dimensions. Most of multi-bit memory cells use a multi-level threshold voltage storing two or more bits for each threshold voltage representing a different data state. However, a transformation of the multi-bit memory cell, in which each bit is stored in both sides of the charge trap insulation layer of the floating trap type memory cell, is disclosed in the technical article entitled “A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell” by Boaz Eitan, Paolo Pavan, Ilan Bloom, Efraim Aloni, Aviv Frommer, and David Finzi, IEEE Electron Device Letters, Vol. 21 November 2000.
Unlike a nonvolatile memory device with a floating gate, such as a flash memory device, the floating trap type memory device may have a plurality of data storing regions in a charge trap insulation layer (14 of FIG. 1), because charges are injected into a trap zone of the charge trap insulation layer (14 of FIG. 1).
FIG. 4 is a top plan view illustrating a conventional 2-bit programmable nonvolatile memory device.
FIG. 5 is an equivalent circuit diagram of the nonvolatile memory device of FIG. 4.
Referring to FIGS. 4 and 5, the conventional nonvolatile memory device comprises a plurality of parallel bit lines bl disposed in a semiconductor substrate at regular intervals. The bit lines bl are impurity diffused regions formed by injecting impurities into the semiconductor substrate. A plurality of parallel word lines wl cross over the bit lines bl at a right angle there to. Metal interconnections 36 for applying external voltages to each of the bit lines bl are connected through bit line plugs 34. Although not shown in the drawings, a multiple insulation layer (18 of FIG. 1) including a charge trap insulation layer is intervened between each of the word lines wl and the semiconductor substrate.
In the cell array, a pair of adjacent bit lines bl and one word line wl crossing a pair of the bit lines bl constitute a memory cell S2. A pair of bit lines, i.e., first and second bit lines bl1 and bl2, and one word line wl1 are selected to select a memory cell S2. To write a first bit b1, a voltage of 10 to 20V is applied to the selected word line wl, a voltage of 5 to 7V is applied to the first bit line b1, and a ground voltage is applied to the second bit line b2. At this time, hot electrons are generated in the vicinity of the first bit line b1, and the hot electrons are injected into a trap zone of the charge trap insulation layer. As a result, a first bit b1 is written. Likewise, a voltage of 10 to 20V is applied to the selected word line wl1, a voltage of 5 to 7V is applied to the second bit line bl2, and a ground voltage is applied to the first bit line bl1, thereby writing a second bit (b2). Consequently, the first and second bits b1 and b2, i.e., 2 bits are stored in one memory cell. While storing the first and second bits b1 and b2 are stored, other word lines wland other bit lines bl are floated.
A read operation for reading out the first bit b1 comprises applying 3V to the selected word line wl1, applying a ground voltage to the first bit line bl1, and applying a voltage of 1 to 2V to the second bit line bl2. The second bit 2 is read out by applying 3V to the selected word line wl1, applying a ground voltage to the second bit line bl2, and applying a voltage of 1 to 2V to the first bit line bl1.
As illustrated in FIGS. 4 and 5, the conventional 2-bit programmable nonvolatile memory device includes a bit line made of a diffused layer. Accordingly, when a voltage of 1 to 2V is applied to a selected bit line in order to read out a written bit, a long charging time is required for elevating a bit line voltage.